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super sequencer ? with open-loop margining dacs ADM1067 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features complete supervisory and sequencing solution for up to 10 supplies 10 supply fault detectors enable supervision of supplies to <0.5% accuracy at all voltages at 25c <1.0 % accuracy across all voltages and temperatures 5 selectable input attenuators allow supervision supplies up to 14.4 v on vh supplies up to 6 v on vpn (vp1 to vp4) 5 dual-function inputs, vxn (vx1 to vx5) high impedance input to supply fault detector with thresholds between 0.573 v and 1.375 v general-purpose logic input 10 programmable output drivers (pdo1 to pdo10) open collector with external pull-up push/pull output, driven to vddcap or vpn open collector with weak pull-up to vddcap or vpn internally charge-pumped high drive for use with external n-fet (pdo1 to pdo6 only) sequencing engine (se) implements state machine control of pdo outputs state changes conditional on input events enables complex control of boards power-up and power-down sequence control fault event handling interrupt generation on warnings watchdog function can be integrated in se program software control of sequencing through smbus open-loop margining solution for 6 voltage rails 6 voltage output 8-bit dacs (0.300 v to 1.551 v) allow voltage adjustment via dc-to-dc converter trim/feedback node device powered by the highest of vpn, vh for improved redundancy user eeprom: 256 bytes industry-standard 2-wire bus interface (smbus) guaranteed pdo low with vh, vpn = 1.2 v available in 2 packages 40-lead, 6 mm 6 mm lfcsp 48-lead, 7 mm 7 mm tqfp for more information about the ADM1067 register map, refer to the an-698 application note . functional block diagram 04635-001 pdo7 pdo8 pdo9 pdo10 gnd vccp vx1 vx2 vx3 vx4 vx5 vp1 vp2 vp3 vp4 vh sfdgnd vdd arbitrator vddcap programmable reset generators (sfds) dual- function inputs (logic inputs or sfds) sequencing engine configurable output drivers (hv capable of driving gates of n-channel fet) configurable output drivers (lv capable of driving logic signals) pdo1 pdo2 pdo3 pdo4 pdo5 pdo6 sda scl a1 a0 smbus interface eeprom ADM1067 refout refgnd vref dac1 v out dac dac2 v out dac dac3 v out dac dac4 v out dac dac5 v out dac dac6 v out dac mdn mup figure 1. applications central office systems servers/routers multivoltage system line cards dsp/fpga supply sequencing in-circuit testing of margined supplies general description the ADM1067 is a configurable supervisory/sequencing device that offers a single-chip solution for supply monitoring and sequencing in multiple supply systems. in addition to these functions, the ADM1067 integrates six 8-bit voltage output dacs. these circuits can be used to implement an open-loop margining system, which enables supply adjustment by altering either the feedback node or reference of a dc-to-dc converter using the dac outputs. (continued on page 3 )
ADM1067 rev. b | page 2 of 32 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 4 pin configurations and function descriptions ........................... 7 absolute maximum ratings............................................................ 9 thermal resistance ...................................................................... 9 esd caution.................................................................................. 9 typical performance characteristics ........................................... 10 powering the ADM1067 ................................................................ 13 inputs................................................................................................ 14 supply supervision..................................................................... 14 programming the supply fault detectors............................... 14 input comparator hysteresis.................................................... 15 input glitch filtering ................................................................. 15 supply supervision with vxn inputs ...................................... 15 vxn pins as digital inputs........................................................ 15 outputs ............................................................................................ 17 supply sequencing through configurable output drivers .. 17 default output configuration.................................................. 18 sequencing engine ......................................................................... 19 overview...................................................................................... 19 warnings...................................................................................... 19 smbus jump/unconditional jump .......................................... 19 sequencing engine application example ............................... 20 fault and status reporting........................................................ 21 supply margining ........................................................................... 22 overview ..................................................................................... 22 open-loop margining .............................................................. 22 writing to the dacs .................................................................. 22 choosing the size of the attenuation resistor....................... 23 dac limiting/other safety features ...................................... 23 applications diagram .................................................................... 24 communicating with the ADM1067........................................... 25 configuration download at power-up................................... 25 updating the configuration ..................................................... 25 updating the sequencing engine............................................. 26 internal registers........................................................................ 26 eeprom ..................................................................................... 26 serial bus interface..................................................................... 26 smbus protocols for ram and eeprom.............................. 29 write operations ........................................................................ 29 read operations......................................................................... 30 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 11/06rev. a to rev. b updated format..................................................................universal c hanges to features.......................................................................... 1 changes to figure 2.......................................................................... 3 changes to table 1............................................................................ 4 changes to table 2............................................................................ 7 changes to absolute maximum ratings section......................... 9 changes to programming the supply fault detectors section............................................................................ 14 changes to table 6.......................................................................... 14 added the default output configuration section..................... 18 changes to fault reporting section............................................. 21 changes to figure 28...................................................................... 24 changes to the identifying the ADM1067 on the smbus section .................................................................... 26 changes to figure 30 and figure 31............................................. 28 changes to ordering guide .......................................................... 32 1/05rev. 0 to rev. a changes to figure 1...........................................................................1 changes to absolute maximum ratings section..........................8 change to supply sequencing through configurable output drivers section.................................................................. 16 changes to figure 28...................................................................... 22 change to table 9 ........................................................................... 25 10/04revision 0: initial version
ADM1067 rev. b | page 3 of 32 general description (continued from page 1) supply margining can be performed with a minimum of external components. the margining capability can be used for in-circuit testing of a board during production (for example, to verify the board functionality at ?5% of nominal supplies). it can also be used dynamically to accurately control the output voltage of a dc-to-dc converter. the device provides up to 10 programmable inputs for monitoring under, over, or out-of-window faults on up to 10 supplies. in addition, 10 programmable outputs can be used as logic enables. six of them can also provide up to a 12 v output for driving the gate of an n-channel fet that can be placed in the path of a supply. the logical core of the device is a sequencing engine. this state- machine-based construction provides up to 63 different states. this design enables very flexible sequencing of the outputs, based on the condition of the inputs. the device is controlled via configuration data that can be programmed into an eeprom. the whole configuration can be programmed using an intuitive gui-based software package provided by analog devices, inc. 04635-002 gpi signal conditioning sfd gpi signal conditioning sfd sfd sfd selectable attenuator selectable attenuator osc eeprom sda scl a1 a0 smbus interface device controller refout 10f refgnd vref ADM1067 configurable o/p driver (hv) pdo1 pdo2 pdognd gnd pdo3 configurable o/p driver (hv) pdo4 configurable o/p driver (lv) pdo5 pdo6 pdo7 pdo8 pdo9 configurable o/p driver (lv) pdo10 sequencing engine vx2 vx3 vx4 vp2 vp3 vp4 vh vp1 vx1 agnd vx5 vddcap vdd arbitrator vccp reg 5.25v charge pump 10f 10f dac1 v out dac dac2 v out dac dac3 v out dac dac4 v out dac dac5 v out dac dac6 v out dac mdn mup figure 2. detailed block diagram
ADM1067 rev. b | page 4 of 32 specifications vh = 3.0 v to 14.4 v 1 , vpn = 3.0 v to 6.0 v 1 , t a = ?40c to +85c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments power supply arbitration vh, vpn 3.0 v minimum supply required on one of vpn, vh vpn 6.0 v maximum vddcap = 5.1 v, typical vh 14.4 v vddcap = 4.75 v vddcap 2.7 4.75 5.4 v regulated ldo output c vddcap 10 f minimum recommended decoupling capacitance power supply supply current, i vh , i vpn 4.2 6 ma vddcap = 4.75 v, pdo1 to pdo10 off, dacs off, adc off additional currents all pdo fet drivers on 1 ma vddcap = 4.75 v, pdo1 to pdo6 loaded with 1 a each, pdo7 to pdo10 off current available from vddcap 2 ma maximum additional load that can be drawn from all pdo pull-ups to vddcap dacs supply current 2.2 ma 6 dacs on with 100 a maximum load on each adc supply current 1 ma running round-robin loop eeprom erase current 10 ma 1 ms duration only, vddcap = 3 v supply fault detectors vh pin input attenuator error 0.05 % midrange and high range detection ranges high range 6 14.4 v midrange 2.5 6 v vpn pins input attenuator error 0.05 % low range and midrange detection ranges midrange 2.5 6 v low range 1.25 3 v ultralow range 0.573 1.375 v no input attenuation error vxn pins input impedance 1 m detection ranges ultralow range 0.573 1.375 v no input attenuation error absolute accuracy 1 % vref error + dac nonlinearity + comparator offset error + input attenuation error threshold resolution 8 bits digital glitch filter 0 s minimum programmable filter length 100 s maximum programmable filter length buffered voltage output dacs resolution 8 bits code 0x80 output voltage 6 dacs are individually selectable for centering on one of four output voltage ranges range 1 0.592 0.6 0.603 v range 2 0.796 0.8 0.803 v range 3 0.997 1 1.003 v range 4 1.247 1.25 1.253 v output voltage range 601.25 mv same range, independent of center point lsb step size 2.36 mv inl 0.75 lsb endpoint corrected dnl 0.4 lsb
ADM1067 rev. b | page 5 of 32 parameter min typ max unit test conditions/comments gain error 1 % maximum load current (source) 100 a maximum load current (sink) 100 a maximum load capacitance 50 pf settling time into 50 pf load 2 s load regulation 2.5 mv per ma psrr 60 db dc 40 db 100 mv step in 20 ns with 50 pf load reference output reference output voltage 2.043 2.048 2.053 v no load load regulation ?0.25 mv sourcing current, i dacnmax = ? 100 a 0.25 mv sinking current, i dacnmax = 100 a minimum load capacitance 1 f capacitor required for decoupling, stability psrr 60 db dc programmable driver outputs high voltage (charge pump) mode (pdo1 to pdo6) output impedance 500 k v oh 11 12.5 14 v i oh = 0 10.5 12 13.5 v i oh = 1 a i outavg 20 a 2 v < v oh < 7 v standard (digital output) mode (pdo1 to pdo10) v oh 2.4 v v pu (pull-up to vddcap or vpn) = 2.7 v, i oh = 0.5 ma 4.5 v v pu to vpn = 6.0 v, i oh = 0 ma v pu ? 0.3 v v pu 2.7 v, i oh = 0.5 ma v ol 0 0.50 v i ol = 20 ma i ol 2 20 ma maximum sink current per pdo pin i sink 2 60 ma maximum total sink for all pdos r pull-up 16 20 29 k internal pull-up i source (vpn) 2 2 ma current load on any vpn pull-ups, that is, total source current available through any number of pdo pull-up switches configured onto any one three-state output leakage current 10 a v pdo = 14.4 v oscillator frequency 90 100 110 khz all on-chip time delays derived from this clock digital inputs (vxn, a0, a1, mup, mdn) input high voltage, v ih 2.0 v maximum v in = 5.5 v input low voltage, v il 0.8 v maximum v in = 5.5 v input high current, i ih ?1 a v in = 5.5 v input low current, i il 1 a v in = 0 input capacitance 5 pf programmable pull-down current, i pull-down 20 a vddcap = 4.75, t a = 25c, if known logic state is required serial bus digital inputs (sda, scl) input high voltage, v ih 2.0 v input low voltage, v il 0.8 v output low voltage, v ol 2 0.4 v i out = ?3.0 ma serial bus timing clock frequency, f sclk 400 khz bus free time, t buf 4.7 s start setup time, t su;sta 4.7 s start hold time, t hd;sta 4 s scl low time, t low 4.7 s
ADM1067 rev. b | page 6 of 32 parameter min typ max unit test conditions/comments scl high time, t high 4 s scl, sda rise time, t r 1000 s scl, sda fall time, t f 300 s data setup time, t su;dat 250 ns data hold time, t hd;dat 5 ns input low current, i il 1 a v in = 0 sequencing engine timing state change time 10 s 1 at least one of the vh, vpn pins must be 3.0 v to maintain the device supply on vddcap. 2 specification is not production tested, but is supported by characterization data at initial product release.
ADM1067 rev. b | page 7 of 32 pin configurations and function descriptions 04635-003 nc = no connect ADM1067 top view (not to scale) gnd 40 vddcap 39 mdn 38 mup 37 sda 36 scl 35 a1 34 a0 33 vccp 32 pdognd 31 agnd 11 refgnd 12 nc 13 refout 14 dac1 15 dac2 16 dac3 17 dac4 18 dac5 19 dac6 20 v x1 1 v x2 2 v x3 3 v x4 4 v x5 5 v p1 6 v p2 7 v p3 8 v p4 9 vh 10 pdo1 30 pdo2 29 pdo3 28 pdo4 27 pdo5 26 pdo6 25 pdo7 24 pdo8 23 pdo9 22 pdo10 21 pin 1 indicator figure 3. lfcsp pin configuration 04635-004 nc = no connect nc 48 gnd 47 vddcap 46 mdn 45 mup 44 sda 43 scl 42 a1 41 a0 40 vccp 39 pdognd 38 nc 37 nc 13 agnd 14 refgnd 15 nc 16 refout 17 dac1 18 dac2 19 dac3 20 dac4 21 dac5 22 dac6 23 nc 24 nc 1 v x1 2 v x2 3 v x3 4 v x4 5 v x5 6 v p1 7 v p2 8 v p3 9 v p4 10 vh 11 nc 12 nc 36 pdo1 35 pdo2 34 pdo3 33 pdo4 32 pdo5 31 pdo6 30 pdo7 29 pdo8 28 pdo9 27 pdo10 26 nc 25 ADM1067 top view (not to scale) pin 1 indicator figure 4. tqfp pin configuration table 2. pin function descriptions pin number lfcsp 1 tqfp mnemonic description 13 1, 12, 13, 16, 24, 25, 36, 37, 48 nc no connection. 1 to 5 2 to 6 vx1 to vx5 (vxn) high impedance inputs to supply fault detectors. fault thresholds can be set from 0.573 v to 1.375 v. alternatively, these pins can be used as general-purpose digital inputs. 6 to 9 7 to 10 vp1 to vp4 (vpn) low voltage inputs to supply fault detectors. thr ee input ranges can be set by altering the input attenuation on a potential divider connected to these pins, the output of which connects to a supply fault detector. these pins allow thresholds from 2.5 v to 6.0 v, 1.25 v to 3.00 v, and 0.573 v to 1.375 v. 10 11 vh high voltage input to supply fault detectors. thr ee input ranges can be set by altering the input attenuation on a potential divider connected to this pin, the output of which connects to a supply fault detector. this pin allows thresholds from 6.0 v to 14.4 v and 2.5 v to 6.0 v. 11 14 agnd 2 ground return for input attenuators. 12 15 refgnd 2 ground return for on-chip reference circuits. 14 17 refout 2.048 v reference output. note that the capaci tor must be connected between this pin and refgnd. a 10 f capacitor is recommended for this purpose. 15 to 20 18 to 23 dac1 to dac6 voltage output dacs. these pins defaul t to high impedance at power-up. 21 to 30 26 to 35 pdo10 to pdo1 programmable output drivers. 31 38 pdognd 2 ground return for output drivers. 32 39 vccp central charge-pump voltage of 5.25 v. a reservoir capacitor must be connected between this pin and gnd. a 10 f capacitor is recommended for this purpose. 33 40 a0 logic input. this pin sets the seventh bit of the smbus interface address. 34 41 a1 logic input. this pin sets the sixth bit of the smbus interface address. 35 42 scl smbus clock pin. open-drain output requires external resistive pull-up. 36 43 sda smbus data i/o pin. open-drain output requires external resistive pull-up. 37 44 mup digital input. forces dacs to their lowest value, causing the voltage at the feedback node to drop. this is compensated for by an increase in th e supply output voltage, thus margining up.
ADM1067 rev. b | page 8 of 32 pin number lfcsp 1 tqfp mnemonic description 38 45 mdn digital input. forces dacs to their highest value, causing the voltage at the feedback node to rise. this is compensated for by a decrease in the supply output voltage, thus margining down. 39 46 vddcap device supply voltage. linearly regulated from the highest of the vpn, vh pins to a typical of 4.75 v. note that the capacitor must be connected betw een this pin and gnd. a 10 f capacitor is recommended for this purpose. 40 47 gnd 2 supply ground. 1 note that the lfcsp has an exposed pad on the bottom. this pad is a no connect (nc). if possible, this pad should be soldered to the board for improved mechanical stability. 2 in a typical application, all ground pins are connected together.
ADM1067 rev. b | page 9 of 32 absolute maximum ratings table 3. parameter rating voltage on vh pin 16 v voltage on vpn pins 7 v voltage on vxn pins ?0.3 v to +6.5 v voltage on a0, a1 pins ?0.3 v to +7 v voltage on refout pin 5 v voltage on vddcap, vccp pins 6.5 v voltage on dacn pins 6.5 v voltage on pdon pins 16 v voltage on sda, scl pins 7 v voltage on gnd, agnd, pdognd, refgnd pins ?0.3 v to +0.3 v voltage on mup and mdn pins vddcap + 0.6 v input current at any pin 5 ma package input current 20 ma maximum junction temperature (t j max) 150c storage temperature range ?65c to +150c lead temperature soldering vapor phase, 60 sec 215c esd rating, all pins 2000 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja unit 40-lead lfcsp 25 c/w 48-lead tqfp 50 c/w esd caution
ADM1067 rev. b | page 10 of 32 typical performance characteristics 6 0 1 2 3 4 5 06 5 4 3 2 1 04635-050 v vp1 (v) v vddcap (v) figure 5. v vddcap vs. v vp1 6 0 1 2 3 4 5 01 6 1412108642 04635-051 v vh (v) v vddcap (v) figure 6. v vddcap vs. v vh 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0123456 04635-052 v vp1 (v) i vp1 (ma) figure 7. i vp1 vs. v vp1 (vp1 as supply) 180 160 140 120 100 80 60 40 20 0 0123456 04635-053 v vp1 (v) i vp1 ( a) figure 8. i vp1 vs. v vp1 (vp1 not as supply) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 01 6 1412108642 04635-054 v vh (v) i vh (ma) figure 9. i vh vs. v vh (vh as supply) 350 300 250 200 150 100 50 0 06 5 4 3 2 1 04635-055 v vh (v) i vh ( a) figure 10. i vh vs. v vh (vh not as supply)
ADM1067 rev. b | page 11 of 32 14 12 10 8 6 4 2 0 0 15.0 12.5 10.0 7.5 5.0 2.5 04635-056 i load current ( a) v pdo1 charge pumped figure 11. v pdo1 (fet drive mode) vs. i load 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 06 5 4 3 2 1 04635-057 i load (ma) v pdo1 (v) vp1 = 5v vp1 = 3v figure 12. v pdo1 (strong pull-up to vp) vs. i load 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 06 0 50 40 30 20 10 04635-058 i load ( a) v pdo1 (v) vp1 = 5v vp1 = 3v figure 13. v pdo1 (weak pull-up to vp) vs. i load 04635-059 ch1 200mv m1.00 s ch1 756mv 1 dac buffer output probe point 47pf 20k figure 14. transient response of dac code change into typical load 04635-060 ch1 200mv m1.00 s ch1 944mv 1 dac buffer output 1v probe point 100k figure 15. transient response of dac to turn-on from hi-z state 1.005 1.004 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 ?40 ?20 0 20 40 60 100 80 04635-065 temperature ( c) dac output vp1 = 3.0v vp1 = 4.75v figure 16. dac output vs. temperature
ADM1067 rev. b | page 12 of 32 2.058 2.038 2.043 2.048 2.053 ?40 ?20 0 20 40 60 100 80 04635-061 temperature ( c) refout (v) vp1 = 3.0v vp1 = 4.75v figure 17. refout vs. temperature
ADM1067 rev. b | page 13 of 32 powering the ADM1067 the ADM1067 is powered from the highest voltage input on either the positive-only supply inputs (vpn) or the high voltage supply input (vh). this technique offers improved redundancy, because the device is not dependent on any particular voltage rail to keep it operational. the same pins are used for supply fault detection (discussed in the supply supervision section). a vdd arbitrator on the device chooses which supply to use. the arbitrator can be considered an oring of five ldos together. a supply comparator chooses the highest input to provide the on- chip supply. there is minimal switching loss with this architecture (~0.2 v), resulting in the ability to power the ADM1067 from a supply as low as 3.0 v. note that the supply on the vxn pins cannot be used to power the device. an external capacitor to gnd is required to decouple the on- chip supply from noise. this capacitor should be connected to the vddcap pin, as shown in figure 18 . the capacitor has another use during brownouts (momentary loss of power). under these conditions, when the input supply (vpn or vh) dips transiently below v dd , the synchronous rectifier switch immediately turns off so that it does not pull v dd down. the v dd capacitor can then act as a reservoir to keep the device active until the next highest supply takes over the powering of the device. a 10 f capacitor is recommended for this reservoir/decoupling function. note that when two or more supplies are within 100 mv of each other, the supply that first takes control of v dd keeps control. for example, if vp1 is connected to a 3.3 v supply, v dd powers up to approximately 3.1 v through vp1. if vp2 is then connected to another 3.3 v supply, vp1 still powers the device, unless vp2 goes 100 mv higher than vp1. supply comparator in en out 4.75v ldo in en out 4.75v ldo in en out 4.75v ldo in en out 4.75v ldo in en out 4.75v ldo vh vp4 vp3 vp2 vp1 vddcap internal device supply 0 4635-022 figure 18. vdd arbitrator operation
ADM1067 rev. b | page 14 of 32 inputs supply supervision the ADM1067 has 10 programmable inputs. five of these are dedicated supply fault detectors (sfds). these dedicated inputs are called vh and vpn (vp1 to vp4) by default. the other five inputs are labeled vxn (vx1 to vx5) and have dual functionality. they can be used as either supply fault detectors, with similar functionality as vh and vpn, or cmos-/ttl- compatible logic inputs to the devices. therefore, the ADM1067 can have up to 10 analog inputs, a minimum of five analog inputs and five digital inputs, or a combination. if an input is used as an analog input, it cannot be used as a digital input. therefore, a configuration requiring 10 analog inputs has no available digital inputs. table 6 shows the details of each of the inputs. 04635-023 + ? + ? uv comparator vref fault type select ov comparator fault output glitch filter vpn mid low rang e select ultra low figure 19. supply fault detector block programming the supply fault detectors the ADM1067 has up to 10 supply fault detectors (sfds) on its 10 input channels. these highly programmable reset generators enable the supervision of up to 10 supply voltages. the supplies can be as low as 0.573 v and as high as 14.4 v. the inputs can be configured to detect an undervoltage fault (the input voltage drops below a preprogrammed value), an overvoltage fault (the input voltage rises above a preprogrammed value) or an out-of- window fault (undervoltage or overvoltage). the thresholds can be programmed to an 8-bit resolu tion in registers provided in the ADM1067. this translates to a voltage resolution that is dependent on the range selected. the resolution is given by step size = t hreshold range /255 therefore, if the high range is selected on vh, the step size can be calculated as follows: (14.4 v ? 6.0 v)/255 = 32.9 mv table 5 lists the upper and lower limit of each available range, the bottom of each range (v b ), and the range itself (v r ). table 5. voltage range limits voltage range (v) v b (v) v r (v) 0.573 to 1.375 0.573 0.802 1.25 to 3.00 1.25 1.75 2.5 to 6.0 2.5 3.5 6.0 to 14.4 6.0 9.6 the threshold value required is given by v t = ( v r n )/255 + v b where: v t is the desired threshold voltage (uv or ov). v r is the voltage range. n is the decimal value of the 8-bit code. v b is the bottom of the range. reversing the equation, the code for a desired threshold is given by n = 255 (v t ? v b )/ v r for example, if the user wants to set a 5 v ov threshold on vp1, the code to be programmed in the ps1ovth register (discussed in the an-698 application note ) is given by n = 255 (5 ? 2.5)/3.5 therefore, n = 182 (1011 0110 or 0xb6). table 6. input functions, thresholds, and ranges input function voltage range (v) maximum hysteresis voltage resolution (mv) glitch filter (s) vh high v analog input 2.5 to 6.0 425 mv 13.7 0 to 100 6.0 to 14.4 1.02 v 32.9 0 to 100 vpn positive analog input 0.573 to 1.375 97.5 mv 3.14 0 to 100 1.25 to 3.00 212 mv 6.8 0 to 100 2.5 to 6.0 425 mv 13.7 0 to 100 vxn high-z analog input 0.573 to 1.375 97.5 mv 3.14 0 to 100 digital input 0 to 5 n/a n/a 0 to 100
ADM1067 rev. b | page 15 of 32 input comparator hysteresis the uv and ov comparators shown in figure 19 are always looking at vpn. to avoid chattering (multiple transitions when the input is very close to the set threshold level), these compara- tors have digitally programmable hysteresis. the hysteresis can be programmed up to the values shown in tabl e 6 . the hysteresis is added after a supply voltage goes out of tolerance. therefore, the user can program how much above the uv threshold the input must rise again before a uv fault is deasserted. similarly, the user can program how much below the ov threshold an input must fall again before an ov fault is deasserted. the hysteresis figure is given by v hyst = v r n thresh /255 where: v hyst is the desired hysteresis voltage. n thresh is the decimal value of the 5-bit hysteresis code. note that n thresh has a maximum value of 31. the maximum hysteresis for the ranges is listed in table 6 . input glitch filtering the final stage of the sfds is a glitch filter. this block provides time-domain filtering on the output of the sfd comparators, allowing the user to remove any spurious transitions such as supply bounce at turn-on. the glitch filter function is additional to the digitally programmable hysteresis of the sfd compara- tors. the glitch filter timeout is programmable up to 100 s. for example, when the glitch filter timeout is 100 s, any pulses appearing on the input of the glitch filter block that are less than 100 s in duration are prevented from appearing on the output of the glitch filter block. any input pulse that is longer than 100 s appears on the output of the glitch filter block. the output is delayed with respect to the input by 100 s. the filtering process is shown in figure 20 . 04635-024 t 0 t gf t 0 t gf t 0 t gf t 0 t gf input input pulse shorter than glitch filter timeout input pulse longer than glitch filter timeout output programmed timeout programmed timeout input output figure 20. input glitch filter function supply supervision with vxn inputs the vxn inputs have two functions. they can be used as either supply fault detectors or digital logic inputs. when selected as an analog (sfd) input, the vxn pins have very similar functionality to the vh and vpn pins. the major difference is that the vxn pins have only one input range: 0.573 v to 1.375 v. therefore, these inputs can directly supervise only the very low supplies. however, the input impedance of the vxn pins is high, allowing an external resistor divide network to be connected to the pin. thus, any supply can be potentially divided down into the input range of the vxn pin and be supervised. this enables the ADM1067 to monitor other supplies such as +24 v, +48 v, and ?5 v. an additional supply supervision function is available when the vxn pins are selected as digital inputs. in this case, the analog function is available as a second detector on each of the dedi- cated analog inputs, vpn and vh. the analog function of vx1 is mapped to vp1, vx2 is mapped to vp2, and so on. vx5 is mapped to vh. in this case, these sfds can be viewed as a secondary or warning sfd. the secondary sfds are fixed to the same input range as the primary sfd. they are used to indicate warning levels rather than failure levels. this allows faults and warnings to be generated on a single supply using only one pin. for example, if vp1 is set to output a fault if a 3.3 v supply drops to 3.0 v, vx1 can be set to output a warning at 3.1 v. warning outputs are available for readback from the status registers. they are also ored together and fed into the sequencing engine (se), allowing warnings to generate interrupts on the pdos. therefore, in this example, if the supply drops to 3.1 v, a warning is generated, and remedial action can be taken before the supply drops out of tolerance. vxn pins as digital inputs as mentioned in the supply supervision with vx n inputs section, the vxn input pins on the ADM1067 have dual func- tionality. the second function is as a digital input to the device. therefore, the ADM1067 can be configured for up to five digital inputs. these inputs are ttl-/cmos- compatible. standard logic signals can be applied to the pins: reset from reset generators, pwrgd signals, fault flags, manual resets, and so on. these signals are available as inputs to the se, and therefore, can be used to control the status of the pdos. the inputs can be configured to detect either a change in level or an edge. when configured for level detection, the output of the digital block is a buffered version of the input. when configured for edge detection, once the logic transition is detected, a pulse of programmable width is output from the digital block. the width is programmable from 0 s to 100 s.
ADM1067 rev. b | page 16 of 32 the digital blocks feature the same glitch filter function that is available on the sfds. this enables the user to ignore spurious transitions on the inputs. for example, the filter can be used to debounce a manual reset switch. when configured as digital inputs, each vxn pin has a weak (10 a) pull-down current source available for placing the input in a known condition, even if left floating. the current source, if selected, weakly pulls the input to gnd. 04635-027 detector vxn (digital input) glitch filter vref = 1.4v to sequencing engine + ? figure 21. vxn digital input function
ADM1067 rev. b | page 17 of 32 outputs supply sequencing through configurable output drivers supply sequencing is achieved with the ADM1067 using the programmable driver outputs (pdos) on the device as control signals for supplies. the output drivers can be used as logic enables or as fet drivers. the sequence in which the pdos are asserted (and, therefore, the supplies are turned on) is controlled by the sequencing engine (se). the se determines what action is to be taken with the pdos based on the condition of the ADM1067 inputs. therefore, the pdos can be set up to assert when the sfds are in tolerance, the correct input signals are received on the vxn digital pins, no warnings are received from any of the inputs of the device, and so on. the pdos can be used for a variety of functions. the primary function is to provide enable signals for ldos or dc-to-dc converters that generate supplies locally on a board. the pdos can also be used to provide a power_good signal when all the sfds are in tolerance, or a reset output if one of the sfds goes out of specification (this can be used as a status signal for a dsp, fpga, or other microcontroller). the pdos can be programmed to pull up to a number of different options. the outputs can be programmed as follows: ? open-drain (allowing the user to connect an external pull- up resistor) ? open-drain with weak pull-up to v dd ? open-drain with strong pull-up to v dd ? open-drain with weak pull-up to vpn ? open-drain with strong pull-up to vpn ? strong pull-down to gnd ? internally charge-pumped high drive (12 v, pdo1 to pdo6 only) the last option (available only on pdo1 to pdo6) allows the user to directly drive a voltage high enough to fully enhance an external n-fet, which is used to isolate, for example, a card- side voltage from a backplane supply (a pdo can sustain greater than 10.5 v into a 1 a load). the pull-down switches can also be used to drive status leds directly. the data driving each of the pdos can come from one of three sources. the source can be enabled in the pdoncfg configu- ration register (see the an-698 application note for details). the data sources are as follows: ? output from the se. ? directly from the smbus. a pdo can be configured so the smbus has direct control over it. this enables software control of the pdos. therefore, a microcontroller can be used to initiate a software power-up/power-down sequence. ? on-chip clock. a 100 khz clock is generated on the device. this clock can be made available on any of the pdos. it can be used, for example, to clock an external device such as an led. pdo se data cfg4 cfg5 cfg6 smbus data clk data 10? 20k ? 10? 20k ? vp1 sel vp4 10? 20k ? v dd v fet (pdo1 to pdo6 only) 20k? 04635-028 figure 22. programmable driver output
ADM1067 rev. b | page 18 of 32 default output configuration all of the internal registers in an unprogrammed ADM1067 device from the factory are set to 0. because of this, the pdos are pulled to gnd by a weak (20 k) on-chip pull-down resistor. all pdos behave as follows as the input supply to the ADM1067 ramps up on vpn or vh: ? input supply 0 v to 1 v. pdos high impedance. ? input supply 1 v to 2.7 v. pdos pulled to gnd by a weak (20 k) on-chip pull-down resistor. ? supply > 2.7 v. factory programmed devices continue to pull all pdos to gnd by a weak (20 k) on-chip pull-down resistor. programmed devices download current eeprom configuration data and the programmed setup is latched. pdo then goes to the state demanded by the configuration. this provides a known condition for the pdos during power-up. the internal pull-down can be overdriven with an external pull- up of suitable value tied from the pdo pin to the required pull-up voltage. the 20 k resistor must be accounted for in calculating a suitable value. for example, if pdon must be pulled up to 3.3 v, and 5 v is available as an external supply, the pull-up resistor value is given by 3.3 v = 5 v 20 k/( r up + 20 k) therefore, r up = (100 k ? 66 k)/3.3 v = 10 k
ADM1067 rev. b | page 19 of 32 sequencing engine overview the ADM1067s sequencing engine (se) provides the user with powerful and flexible control of sequencing. the se implements a state machine control of the pdo outputs, with state changes conditional on input events. se programs can enable complex control of boards such as power-up and power-down sequence control, fault event handling, interrupt generation on warnings, among others. a watchdog function that verifies the continued operation of a processor clock can be integrated into the se program. the se can also be controlled via the smbus, giving software or firmware control of the board sequencing. the se state machine comprises 63 state cells. each state has the following attributes: ? monitors signals indicating the status of the 10 input pins, vp1 to vp4, vh, and vx1 to vx5. ? can be entered from any other state. ? three exit routes move the state machine onto a next state: sequence detection, fault monitoring, and timeout. ? delay timers for the sequence and timeout blocks can be programmed independently and changed with each state change. the range of timeouts is from 0 ms to 400 ms. ? output condition of the 10 pdo pins is defined and fixed within a state. ? transition from one state to the next is made in less than 20 s, which is the time needed to download a state definition from eeprom to the se. 04635-029 sequence timeout monitor fault state figure 23. state cell the ADM1067 offers up to 63 state definitions. the signals monitored to indicate the status of the input pins are the outputs of the sfds. warnings the se also monitors warnings. these warnings can be generated when the adc readings violate their limit register value or when secondary voltage monitors on vpn or vh are triggered. the warnings are ored together and are available as a single warning input to each of the three blocks that enable exiting from a state. smbus jump/unconditional jump the se can be forced to advance to the next state uncondition- ally. this enables the user to force the se to advance. examples of where this could be used include moving to a margining state or debugging a sequence. the smbus jump or go-to command can be seen as another input to sequence and timeout blocks, which provide an exit from each state. table 7. sample sequence state entries state sequence timeout monitor idle1 if vx1 is low , go to state idle2. idle2 if vp1 is okay, go to state en3v3. en3v3 if vp2 is okay, go to state en2v5. if vp2 is not okay after 10 ms, go to state dis3v3. if vp1 is not okay, go to state idle1. dis3v3 if vx1 is high, go to state idle1. en2v5 if vp3 is okay, go to state pwrgd. if vp3 is not okay after 20 ms, go to state dis2v5. if vp1 or vp2 is not okay, go to state fsel2. dis2v5 if vx1 is high, go to state idle1. fsel1 if vp3 is not okay, go to state dis2v5. if vp1 or vp2 is not okay, go to state fsel2. fsel2 if vp2 is not okay, go to state dis3v3. if vp1 is not okay, go to state idle1. pwrgd if vx1 is high, go to state dis2v5. if vp1, vp2, or vp3 is not okay, go to state fsel1.
ADM1067 rev. b | page 20 of 32 sequencing engine application example the application in this section demonstrates the operation of the sequencing engine (se). figure 24 shows how the simple building block of a single se state can be used to build a power- up sequence for a 3-supply system. table 8 lists the pdo outputs for each state in the same se implementation. in this system, the presence of a good 5 v supply on vp1 and the vx1 pin held low are the triggers required for a power-up sequence to start. the sequence next intends to turn on the 3.3 v supply, and then the 2.5 v supply (assuming successful turn-on of the 3.3 v supply). once all three supplies are good, the pwrgd state is entered, where the se remains until a fault occurs on one of the three supplies or until it is instructed to go through a power-down sequence by vx1 going high. 04635-030 idle1 idle2 en3v3 dis3v3 dis2v5 pwrgd fsel1 fsel2 sequence states monitor fault states timeout states vx1 = 0 vp1 = 1 vp1 = 0 (vp1 + vp2) = 0 (vp1 + vp2 + vp3) = 0 (vp1 + vp2) = 0 vp2 = 1 vp3 = 1 vp2 = 0 vx1 = 1 vp3 = 0 vp2 = 0 vp1 = 0 vx1 = 1 vx1 = 1 10ms 20ms en2v5 figure 24. sample application flow diagram faults are dealt with throughout the power-up sequence on a case-by-case basis. the following three sections describe the individual blocks and use the sample application in figure 24 to demonstrate the state machines actions. sequence detector the sequence detector block is used to detect when a step in a sequence has been completed. it looks for one of the se inputs to change state, and is most often used as the gate on successful progress through a power-up or power-down sequence. a timer block that is included in this detector can insert delays into a power-up or power-down sequence, if required. timer delays can be set from 10 s to 400 ms. figure 25 is a block diagram of the sequence detector. 04635-032 supply fault detection logic input change or fault detection warnings force flow (unconditional jump) vp1 vx5 invert sequence detector select timer figure 25. sequence detector block diagram the sequence detector can also help to identify monitoring faults. in the sample application shown in figure 24 , the fsel1 and fsel2 states first identify which of the vp1, vp2, or vp3 pins has faulted, and then they take the appropriate action. monitoring fault detector the monitoring fault detector block is used to detect a failure on an input. the logical function implementing this is a wide or gate, which can detect when an input deviates from its expected condition. the clearest demonstration of the use of this block is in the pwrgd state, where the monitor block indicates that a failure on one or more of the vp1, vp2, or vp3 inputs has occurred. no programmable delay is available in this block because the triggering of a fault condition is likely to be caused by a supply falling out of tolerance. in this situation, the user needs to react as quickly as possible. some latency occurs when moving out of this state, however, because it takes a finite amount of time (~20 s) for the state configuration to download from eeprom into the se. figure 26 is a block diagram of the monitoring fault detector. table 8. pdo outputs for each state pdo outputs idle1 idle2 en3v3 en2v5 dis3v3 dis2v5 pwrgd fsel1 fsel2 pdo1 = 3v3on 0 0 1 1 0 1 1 1 1 pdo2 = 2v5on 0 0 0 1 1 0 1 1 1 pdo3 = fault 0 0 0 0 1 1 0 1 1
ADM1067 rev. b | page 21 of 32 04635-033 supply fault detection logic input change or fault detection v p1 v x5 monitoring fault detector mask sense 1-bit fault detector fault warnings mask 1-bit fault detector fault mask sense 1-bit fault detector fault figure 26. monitoring fault detector block diagram timeout detector the timeout detector allows the user to trap a failure to make proper progress through a power-up or power-down sequence. in the sample application shown in figure 24 , the timeout next- state transition is from the en3v3 and en2v5 states. for the en3v3 state, the signal 3v3on is asserted upon entry to this state (on the pdo1 output pin) to turn on a 3.3 v supply. this supply rail is connected to the vp2 pin, and the sequence detec- tor looks for the vp2 pin to go above its uv threshold, which is set in the supply fault detector (sfd) attached to that pin. the power-up sequence progresses when this change is detected. if, however, the supply fails (perhaps due to a short circuit overloading this supply), the timeout block traps the problem. in this example, if the 3.3 v supply fails within 10 ms, the se moves to the dis3v3 state and turns off this supply by bringing pdo1 low. it also indicates that a fault has occurred by taking pdo3 high. timeout delays from 100 s to 400 ms can be programmed. fault and status reporting the ADM1067 has a fault latch for recording faults. two registers are set aside for this purpose, fstat1 and fstat2. a single bit is assigned to each input of the device, and a fault on that input sets the relevant bit. the contents of the fault register can be read out over the smbus to determine which input(s) faulted. the fault register can be enabled/disabled in each state. to latch data from one state, simply ensure that the fault latch is disabled in the following state. this ensures that only real faults are captured and not, for example, undervoltage conditions that may be present during a power-up or power-down sequence. the ADM1067 also has a number of status registers. these include more detailed information, such as whether an undervoltage or overvoltage fault is present on a particular input faulted, as well as information on adc limit faults. note that the data in the status registers is not latched in any way and, therefore, is subject to change at any time. see the an-698 application note for full details about the ADM1067 registers.
ADM1067 rev. b | page 22 of 32 supply margining overview it is often necessary for the system designer to adjust supplies, either to optimize their level or force them away from nominal values to characterize the system performance under these conditions. this is a function typically performed during an in- circuit test (ict), such as when the manufacturer wants to guarantee that the product under test functions correctly at nominal supplies minus 10%. open-loop margining the simplest method of margining a supply is to implement an open-loop technique. a popular method for this is to switch extra resistors into the feedback node of a power module, such as a dc-to-dc converter or low dropout regulator (ldo). the extra resistor alters the voltage at the feedback or trim node and forces the output voltage to margin up or down by a certain amount. the ADM1067 can perform open-loop margining for up to six supplies. the six on-board voltage dacs (dac1 to dac6) can drive into the feedback pins of the power modules to be margined. the simplest circuit to implement this function is an attenuation resistor that connects the dacn pin to the feedback node of a dc-to-dc converter. when the dacn output voltage is set equal to the feedback voltage, no current flows into the attenuation resistor, and the dc-to-dc output voltage does not change. taking dacn above the feedback voltage forces current into the feedback node, and the output of the dc-to-dc converter is forced to fall to compensate for this. the dc-to-dc output can be forced high by setting the dacn output voltage lower than the feedback node voltage. the series resistor can be split in two, and the node between them decoupled with a capacitor to ground. this can help to decouple any noise picked up from the board. decoupling to a ground local to the dc-to- dc converter is recommended. 04635-067 output dc/dc converter feedback gnd attenuation resistor pcb trace noise decoupling capacitor ADM1067 dacoutn v out dac controller vin device controller (smbus) figure 27. open-loop margining system using the ADM1067 the ADM1067 can be commanded to margin a supply up or down over the smbus by updating the values on the relevant dac output. to implement open-loop margining: 1. disable the six dac outputs. 2. set the dac output voltage equal to the voltage on the feedback node. 3. enable the dac. 4. assert mup (drive logic high). the dac voltage moves down to the value set in the dnlim register (see the an-698 application note ). the output of the dc-to-dc converter rises to compensate for this, that is, margin up. 5. assert mdn (drive logic high). the dac voltage moves down to the value set in the dplim register (see the an-698 application note ). the output of the dc-to-dc converter drops to compensate for this, that is, margin down. steps 1 to 3 ensure that when the dacn output buffer is turned on, it has little effect on the dc-to-dc output. the dac output buffer is designed to power up without glitching. it does this by first powering up the buffer to follow the pin voltage and does not drive out onto the pin at this time. once the output buffer is properly enabled, the buffer input is switched over to the dac, and the output stage of the buffer is turned on. output glitching is negligible. the margining method above assumes that margin up and mar- gin down dac limits have been preloaded into the ADM1067 and that only one margin up and margin down level are required. alternatively, a dacn output level can be dynamically altered by an smbus write to that dacn output register. writing to the dacs four dac ranges are offered. they can be placed with midcode (code 0x7f) at 0.6 v, 0.8 v, 1.0 v, and 1.25 v. these voltages are placed to correspond to the most common feedback voltages. centering the dac outputs in this way provides the best use of the dac resolution. for most supplies, it is possible to place the dac midcode at the point where the dc-to-dc output is not modified, thereby giving half of the dac range to margin up and the other half to margin down. the dac output voltage is set by the code written to the dacn register. the voltage is linear with the unsigned binary number in this register. code 0x7f is placed at the midcode voltage, as described previously. the output voltage is given by the following equation: dac output = ( dacn ? 0x7f)/255 0.6015 + v off where v off is one of the four offset voltages.
ADM1067 rev. b | page 23 of 32 there are 256 dac settings available. the midcode value is located at dac code 0x7f, as close as possible to the middle of the 256 code range. the full output swing of the dacs is +302 mv (+128 codes) and ?300 mv (?127 codes) around the selected midcode voltage. the voltage range for each midcode voltage is shown in table 9 . table 9. ranges for midcode voltages midcode voltage (v) minimum voltage output (v) maximum voltage output (v) 0.6 0.300 0.902 0.8 0.500 1.102 1.0 0.700 1.302 1.25 0.950 1.552 choosing the size of the attenuation resistor how much this dac voltage swing affects the output voltage of the dc-to-dc converter that is being margined is determined by the size of the attenuation resistor, r3. because the voltage at the feedback pin remains constant, the current flowing from the feedback node to gnd via r2 is a constant. in addition, the feedback node itself is high impedance. this means that the current flowing through r1 is the same as the current flowing through r3. therefore, direct relationship exists between the extra voltage drop across r1 during margining and the voltage drop across r3. this relationship is given by the following equation: ? v out = r3 r1 ( v fb ? v dacout ) where: ? v out is the change in v out . v fb is the voltage at the feedback node of the dc-to-dc converter. v dacout is the voltage output of the margining dac. this equation demonstrates that, if the user wants the output voltage to change by 300 mv, then r1 = r3. if the user wants the output voltage to change by 600 mv, then r1 = 2 r3, and so on. it is best to use the full dac output range to margin a supply. choosing the attenuation resistor in this way provides the most resolution from the dac. in other words, with one dac code change, the smallest effect on the dc-to-dc output voltage is induced. if the resistor is sized up to use a code such as 27(dec) to 227(dec) to move the dc-to-dc output by 5%, then it takes 100 codes to move 5% (each code moves the output by 0.05%). this is beyond the readback accuracy of the adc, but should not prevent the user from building a circuit to use the most resolution. dac limiting/other safety features limit registers (called dplimn and dnlimn) on the device offer the user some protection from firmware bugs, which can cause catastrophic board problems by forcing supplies beyond their allowable output ranges. essentially, the dac code written into the dacn register is clipped such that the code used to set the dac voltage is actually given by dac code = dacn, dacn dnlimn and dacn dplimn = dnlimn, dacn < dnlimn = dplimn, dacn > dplimn in addition, the dac output buffer is three-stated, if dnlimn > dplimn. by programming the limit registers in this way, the user can make it very difficult for the dac output buffers to be turned on at all during normal system operation (these are among the registers downloaded from eeprom at startup).
ADM1067 rev. b | page 24 of 32 applications diagram 3.3v out 3.3v out vh pdo8 pdo9 pdo10 system reset pdo7 signal_valid pdo6 power_good pdo2 dac1* pdo1 pdo5 pdo4 pdo3 en out dc-dc1 in 3.3v out 3v out 5v out 12v out en out dc-dc2 in 2.5v out en out dc-dc3 in en out ldo in 1.8v out 0.9v out 1.2v out 12v in 5v in 3v in margin down mdn margin up mup 5v out vp1 3v out vp2 3.3v out vp3 2.5v out vp4 1.8v out vx1 1.2v out vx2 0.9v out vx3 power_on vx4 reset_l vx5 10f vccp 10f vddcap 10f refout gnd en trim out dc-dc4 in ADM1067 *only one margining circuit shown for clarity. dac1 to dac6 will allow margining for up to six voltage rails. 04635-068 figure 28. applications diagram
ADM1067 rev. b | page 25 of 32 communicating with the ADM1067 configuration downlo ad at power-up the configuration of the ADM1067 (such as uv/ov thresholds, glitch filter timeouts, and pdo configurations) is dictated by the contents of ram. the ram is comprised of digital latches that are local to each of the functions on the device. the latches are double-buffered and have two identical latches, latch a and latch b. therefore, when an update to a function occurs, the contents of latch a are updated first, and then the contents of latch b are updated with identical data. the advantages of this architecture are explained in detail in this section. the two latches are volatile memory and lose their contents at power-down. therefore, the configuration in the ram must be restored at power-up by downloading the contents of the eeprom (nonvolatile memory) to the local latches. this download occurs in steps, as follows: 1. with no power applied to the device, the pdos are high impedance. 2. when 1 v appears on any of the inputs connected to the vdd arbitrator (vh or vpn), the pdos are weakly pulled to gnd with a 20 k impedance. 3. when the supply rises above the undervoltage lockout of the device (uvlo is 2.5 v), the eeprom starts to download to the ram. 4. the eeprom downloads its contents to all latch as. 5. once the contents of the eeprom are completely downloaded to the latch as, the device controller signals all latch as to download to all latch bs simultaneously, completing the configuration download. 6. the first state definition is downloaded from eeprom into the se 0.5 ms after the configuration download completes. note that any attempt to communicate with the device prior to the completion of the download causes the ADM1067 to issue a no acknowledge (nack). updating the configuration after power-up, with all the configuration settings loaded from eeprom into the ram registers, the user may need to alter the configuration of functions on the ADM1067, such as changing the uv or ov limit of an sfd, changing the fault output of an sfd, or adjusting the rise time delay of one of the pdos. the ADM1067 provides several options that allow the user to update the configuration over the smbus interface. the following three options are controlled in the updcfg register: option 1 update the configuration in real time. the user writes to ram across the smbus and the configuration is updated immediately. option 2 update the latch as without updating the latch bs. with this method, the configuration of the ADM1067 remains unchanged and continues to operate in the original setup until the instruction is given to update the latch bs. option 3 change eeprom register contents without changing the ram contents, and then download the revised eeprom contents to the ram registers. again, with this method, the configuration of the ADM1067 remains unchanged and continues to operate in the original setup until the instruction is given to update the ram. the instruction to download from the eeprom in option 3 is also a useful way to restore the original eeprom contents, if revisions to the configuration are unsatisfactory. for example, if the user needs to alter an ov threshold, the ram register can be updated as described in option 1. however, if the user is not satisfied with the change and wants to revert to the original programmed value, the device controller can issue a command to download the eeprom contents to the ram again, as described in option 3, restoring the ADM1067 to its original configuration. the topology of the ADM1067 makes this type of operation possible. the local, volatile registers (ram) are all double- buffered latches. setting bit 0 of the updcfg register to 1 leaves the double-buffered latches open at all times. if bit 0 is set to 0 and a ram write occurs across the smbus, only the first side of the double-buffered latch is written to. the user must then write a 1 to bit 1 of the updcfg register. this generates a pulse to update all the second latches at once. eeprom writes occur in a similar way. the final bit in this register can enable or disable eeprom page erasure. if this bit is set high, the contents of an eeprom page can all be set to 1. if low, the contents of a page cannot be erased, even if the command code for page erasure is programmed across the smbus. the bit map for the updcfg register is shown in the an-698 application note . a flow chart for download at power-up and subsequent configuration updates is shown in figure 29 .
ADM1067 rev. b | page 26 of 32 04635-035 power-up (v cc > 2.5v) eeprom e e p r o m l d d a t a r a m l d u p d smbus device controller latch a latch b function (ov threshold on vp1) figure 29. configuration update flow diagram updating the sequencing engine sequencing engine (se) functions are not updated in the same way as regular configuration latches. the se has its own dedi- cated 512-byte eeprom for storing state definitions, providing 63 individual states with a 64-bit word each (one state is reserved). at power-up, the first state is loaded from the se eeprom into the engine itself. when the conditions of this state are met, the next state is loaded from eeprom into the engine, and so on. the loading of each new state takes approxi- mately 10 s. to alter a state, the required changes must be made directly to eeprom. ram for each state does not exist. the relevant alterations must be made to the 64-bit word, which is then uploaded directly to eeprom. internal registers the ADM1067 contains a large number of data registers. the principal registers are the address pointer register and the configuration registers. address pointer register this register contains the address that selects one of the other internal registers. when writing to the ADM1067, the first byte of data is always a register address that is written to the address pointer register. configuration registers these registers provide control and configuration for various operating parameters of the ADM1067. eeprom the ADM1067 has two 512-byte cells of nonvolatile, electrically erasable, programmable read-only memory (eeprom), from register address 0xf800 to register address 0xfbff. the eeprom is used for permanent storage of data that is not lost when the ADM1067 is powered down. one eeprom cell contains the configuration data of the device; the other contains the state definitions for the se. although referred to as read-only memory, the eeprom can be written to, as well as read from, via the serial bus in exactly the same way as the other registers. the major differences between the eeprom and other registers are as follows: ? an eeprom location must be blank before it can be written to. if it contains data, it must first be erased. ? writing to eeprom is slower than writing to ram. ? writing to the eeprom should be restricted, because it has a limited write/cycle life of typically 10,000 write operations due to the usual eeprom wear-out mechanisms. the first eeprom is split into 16 (0 to 15) pages of 32 bytes each. page 0 to page 6, starting at address 0xf800, hold the con- figuration data for the applications on the ADM1067 (such as the sfds and pdos). these eeprom addresses are the same as the ram register addresses, prefixed by f8. page 7 is reserved. page 8 to page 15 are for customer use. data can be downloaded from eeprom to ram in one of the following ways: ? at power-up, when page 0 to page 6 are downloaded. ? by setting bit 0 of the udownld register (0xd8), which performs a user download of page 0 to page 6. serial bus interface the ADM1067 is controlled via the serial system management bus (smbus) and is connected to this bus as a slave device, under the control of a master device. it takes approximately 1 ms after power-up for the ADM1067 to download from its eeprom. therefore, access to the ADM1067 is restricted until the download is complete. identifying the ADM1067 on the smbus the ADM1067 has a 7-bit serial bus slave address. the device is powered up with a default serial bus address. the five msbs of the address are set to 01111; the two lsbs are determined by the logical states of pin a1 and pin a0. this allows the connection of four ADM1067s to one smbus.
ADM1067 rev. b | page 27 of 32 table 10. serial bus slave address a0 pin a1 pin hex address 7-bit address low low 0x78 0111100x 1 low high 0x7a 0111101x 1 high low 0x7c 0111110x 1 high high 0x7e 0111111x 1 1 x = read/write bit. the address is shown only as the first 7 msbs. the device also has several identification registers (read-only) that can be read across the smbus. tabl e 11 lists these registers with their values and functions. table 11. identification regi ster values and functions name address value function manid 0xf4 0x41 manufacturer id for analog devices revid 0xf5 0x02 silicon revision mark1 0xf6 0x00 software brand mark2 0xf7 0x00 software brand general smbus timing figure 30 , figure 31 , and figure 32 are timing diagrams for general read and write operations using the smbus. the smbus specification defines specific conditions for different types of read and write operations, which are discussed in the wr ite operations section and read operations section. the general smbus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data-line sda, while the serial clock-line scl remains high. this indicates that a data stream follows. all slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, consisting of a 7-bit slave address (msb first) plus an r/ w bit. this bit deter- mines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). the peripheral whose address corresponds to the transmit- ted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and by holding it low during the high period of this clock pulse. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is a 0, the master writes to the slave device. if the r/ w bit is a 1, the master reads from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to- high transition when the clock is high could be interpreted as a stop signal. if the operation is a write operation, the first data byte after the slave address is a command byte. this tells the slave device what to expect next. it could be an instruction telling the slave device to expect a block write, or it could simply be a register address telling the slave where subsequent data is to be written. because data can flow in only one direction, as defined by the r/ w bit, sending a command to a slave device during a read operation is not possible. before a read operation, it could be necessary to perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. 3. when all data bytes have been read or written, stop condi- tions are established. in write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device releases the sda line during the low period before the ninth clock pulse, but the slave device does not pull it low. this is known as no acknowledge. the master then takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition.
ADM1067 rev. b | page 28 of 32 9 04635-036 19 9 1 19 1 start by master ack. by slave ack. by slave ack. by slave ack. by slave frame 2 command code frame 1 slave address frame n data byte frame 3 data byte scl sda r/w stop by master scl (continued) sda (continued) d7 a0a1 1 11 0 1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 figure 30. general smbus write timing diagram 04635-037 19 9 1 19 1 9 start by master ack. by slave ack. by master ack. by master no ack. frame 2 data byte frame 1 slave address frame n data byte frame 3 data byte scl sda r/w stop by master scl (continued) sda (continued) d7 a0a1 1 11 0 1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 figure 31. general smbus read timing diagram 04635-038 scl sda ps s p t su;sto t hd;sta t su;sta t su;dat t hd;dat t hd;sta t high t buf t low t r t f figure 32. serial bus timing diagram
ADM1067 rev. b | page 29 of 32 smbus protocols for ram and eeprom the ADM1067 contains volatile registers (ram) and nonvolatile registers (eeprom). user ram occupies address 0x00 to address 0xdf; eeprom occupies address 0xf800 to address 0xfbff. data can be written to and read from both ram and eeprom as single data bytes. data can be written only to unprogrammed eeprom locations. to write new data to a programmed loca- tion, it must first be erased. eeprom erasure cannot be done at the byte level. the eeprom is arranged as 32 pages of 32 bytes each, and an entire page must be erased. page erasure is enabled by setting bit 2 in the updcfg register (address 0x90) to 1. if this bit is not set, page erasure cannot occur, even if the command byte (0xfe) is programmed across the smbus. write operations the smbus specification defines several protocols for different types of read and write operations. the following abbreviations are used in figure 33 to figure 41 . ? s start ? p stop ? r read ? w write ? a acknowledge ? a no acknowledge the ADM1067 uses the following smbus write protocols. send byte in a send byte operation, the master device sends a single command byte to a slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master asserts a stop condition on sda and the transaction ends. in the ADM1067, the send byte protocol is used for two purposes: ? to write a register address to ram for a subsequent single byte read from the same address, or a block read or write starting at that address, as shown in figure 33 . 04635-039 24 13 5 slave address ram address (0x00 to 0xdf) sw a a 6 p figure 33. setting a ram a ddress for subsequent read ? to erase a page of eeprom memory. eeprom memory can be written to only if it is unprogrammed. before writing to one or more eeprom memory locations that are already programmed, the page or pages containing those locations must first be erased. eeprom memory is erased by writing a command byte. ? the master sends a command code that tells the slave device to erase the page. the ADM1067 command code for a page erasure is 0xfe (1111 1110). note that, for a page erasure to take place, the page address has to be given in the previous write word transaction (see the wr ite byte/word section). in addition, bit 2 in the updcfg register (address 0x90) must be set to 1. 04635-040 24 13 slave address command byte (0xfe) sw a a 5 6 p figure 34. eeprom page erasure as soon as the ADM1067 receives the command byte, page erasure begins. the master device can send a stop command as soon as it sends the command byte. page erasure takes ap- proximately 20 ms. if the ADM1067 is accessed before erasure is complete, it responds with a no acknowledge (nack). write byte/word in a write byte/word operation, the master device sends a command byte and one or two data bytes to the slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master sends a data byte. 7. the slave asserts ack on sda. 8. the master sends a data byte (or asserts a stop condition at this point). 9. the slave asserts ack on sda. 10. the master asserts a stop condition on sda to end the transaction. in the ADM1067, the write byte/word protocol is used for three purposes: ? to write a single byte of data to ram. in this case, the command byte is the ram address from 0x00 to 0xdf and the only data byte is the actual data, as shown in figure 35 . 04635-041 slave address ram address (0x00 to 0xdf) s w a data ap a 24 13 5 76 8 figure 35. single byte write to ram
ADM1067 rev. b | page 30 of 32 8 ? to set up a 2-byte eeprom address for a subsequent read, write, block read, block write, or page erase. in this case, the command byte is the high byte of the eeprom address from 0xf8 to 0xfb. the only data byte is the low byte of the eeprom address, as shown in figure 36 . 04635-042 slave address eeprom address high byte (0xf8 to 0xfb) sw a eeprom address low byte (0x00 to 0xff) ap a 24 13 5 7 6 figure 36. setting an eeprom address because a page consists of 32 bytes, only the 3 msbs of the address low byte are important f or page erasure. the lower five bits of the eeprom address low byte specify the addresses within a page and are ignored during an erase operation. ? to write a single byte of data to eeprom. in this case, the command byte is the high byte of the eeprom address from 0xf8 to 0xfb. the first data byte is the low byte of the eeprom address, and the second data byte is the actual data, as shown in figure 37 . 04635-043 slave address eeprom address high byte (0xf8 to 0xfb) sw a eeprom address low byte (0x00 to 0xff) a a 24 13 5 7 a 9 data 8 6 p 1 0 figure 37. single byte write to eeprom block write in a block write operation, the master device writes a block of data to a slave device. the start address for a block write must have been set previously. in the ADM1067, a send byte opera- tion sets a ram address, and a write byte/word operation sets an eeprom address, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code that tells the slave device to expect a block write. the ADM1067 command code for a block write is 0xfc (1111 1100). 5. the slave asserts ack on sda. 6. the master sends a data byte that tells the slave device how many data bytes are being sent. the smbus specification allows a maximum of 32 data bytes in a block write. 7. the slave asserts ack on sda. 8. the master sends n data bytes. 9. the slave asserts ack on sda after each data byte. 10. the master asserts a stop condition on sda to end the transaction. 04635-044 slave address sw a 2 command 0xfc (block write) 4 13 a 5 byte count 6 a 7 a 9 1 0 a p a data 1 8 data n data 2 figure 38. block write to eeprom or ram unlike some eeprom devices that limit block writes to within a page boundary, there is no limitation on the start address when performing a block write to eeprom, except when ? there must be at least n locations from the start address to the highest eeprom address (0xfbff), to avoid writing to invalid addresses. ? an addresses cross a page boundary. in this case, both pages must be erased before programming. note that the ADM1067 features a clock extend function for writes to eeprom. programming an eeprom byte takes approximately 250 s, which limits the smbus clock for repeated or block write operations. the ADM1067 pulls scl low and extends the clock pulse when it cannot accept any more data. read operations the ADM1067 uses the following smbus read protocols. receive byte in a receive byte operation, the master device receives a single byte from a slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts ack on sda. 4. the master receives a data byte. 5. the master asserts no acknowledge on sda. 6. the master asserts a stop condition on sda, and the transaction ends. in the ADM1067, the receive byte protocol is used to read a single byte of data from a ram or eeprom location whose address has previously been set by a send byte or write byte/word operation, as shown in figure 39 . 04635-045 23 14 5 slave address s r data p a 6 a figure 39. single byte read from eeprom or ram block read in a block read operation, the master device reads a block of data from a slave device. the start address for a block read must have been set previously. in the ADM1067, this is done by a send byte operation to set a ram address, or a write byte/word operation to set an eeprom address. the block read operation itself consists of a send byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes, as follows:
ADM1067 rev. b | page 31 of 32 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code that tells the slave device to expect a block read. the ADM1067 command code for a block read is 0xfd (1111 1101). 5. the slave asserts ack on sda. 6. the master asserts a repeat start condition on sda. 7. the master sends the 7-bit slave address followed by the read bit (high). 8. the slave asserts ack on sda. 9. the ADM1067 sends a byte-count data byte that tells the master how many data bytes to expect. the ADM1067 always returns 32 data bytes (0x20), which is the maximum allowed by the smbus 1.1 specification. 10. the master asserts ack on sda. 11. the master receives 32 data bytes. 12. the master asserts ack on sda after each data byte. 13. the master asserts a stop condition on sda to end the transaction. 04635-046 slave address sw a 2 command 0xfd (block read) 4 13 a 5 s 6 slave address 7 byte count 910 12 11 a ra 8 data 1 data 32 13 a 14 p a figure 40. block read from eeprom or ram error correction the ADM1067 provides the option of issuing a packet error correction (pec) byte after a write to ram, a write to eeprom, a block write to ram/eeprom, or a block read from ram/ eeprom. this enables the user to verify that the data received by or sent from the ADM1067 is correct. the pec byte is an optional byte sent after that last data byte has been written to or read from the ADM1067. the protocol is as follows: 1. the ADM1067 issues a pec byte to the master. the master checks the pec byte and issues another block read, if the pec byte is incorrect. 2. a no acknowledge (nack) is generated after the pec byte to signal the end of the read. note that the pec byte is calculated using crc-8. the frame check sequence (fcs) conforms to crc-8 by the polynomial c ( x ) = x 8 + x 2 + x 1 + 1 see the smbus 1.1 specification for details. an example of a block read with the optional pec byte is shown in figure 41 . 04635-047 slave address sw a 2 command 0xfd (block read) 4 13 a 5 s 6 slave address 7 byte count 910 12 11 a ra 8 data 1 data 32 a 13 pec 14 a 15 p a figure 41. block read from eeprom or ram with pec
ADM1067 rev. b | page 32 of 32 outline dimensions 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bcs sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vjjd-2 figure 42. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40) dimensions shown in millimeters compliant to jedec standards ms-026abc 0.50 bsc lead pitch 0.27 0.22 0.17 9.00 bsc sq 7.00 bsc sq 1.20 max top view (pins down) 1 12 13 25 24 36 37 48 0.75 0.60 0.45 pin 1 view a 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity seating plane 0 min 7 3.5 0 0.15 0.05 view a rotated 90 ccw figure 43. 48-lead thin plastic quad flat package [tqfp] (su-48) dimensions shown in millimeters ordering guide model temperature range package description package option ADM1067acp ?40c to +85c 40-lead lfcsp_vq cp-40 ADM1067acp-reel ?40c to +85c 40-lead lfcsp_vq cp-40 ADM1067acp-reel7 ?40c to +85c 40-lead lfcsp_vq cp-40 ADM1067acpz 1 ?40c to +85c 40-lead lfcsp_vq cp-40 ADM1067asu ?40c to +85c 48-lead tqfp su-48 ADM1067asu-reel ?40c to +85c 48-lead tqfp su-48 ADM1067asu-reel7 ?40c to +85c 48-lead tqfp su-48 ADM1067asuz 1 ?40c to +85c 48-lead tqfp su-48 eval-ADM1067lfeb evaluation kit (lfcsp version) eval-ADM1067tqeb evaluation kit (tqfp version) 1 z = pb-free part. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04635-0-11/06(b)

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